1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and to a method of erasing stored data. More specifically, the present invention relates to a nonvolatile semiconductor memory device such as a flash memory, and to an improved method of erasing stored data.
2. Description of the Background Art
FIG. 13 is a block diagram showing the whole structure of a flash memory as one example of a conventional nonvolatile memory. Referring to FIG. 13, a data input/output terminal 27 is used for input of information to be stored, and for providing stored information from the inside. In case of a flash memory, this terminal is also used for inputting commands. A command is an instruction input to the chip when an operation is to be effected on the chip. The chip determines internal operation in accordance with the command, and performs internal address generation, internal voltage control and so on, for writing or erasing information.
Data input to data input terminal 27 is latched by a data latch 3 through an input buffer 1. The latched information is input to program circuit 17 as a WD signal, and applied to a bit line connected to an arbitrary memory cell in a memory array 19 through a Y gate 9. WD signal is further applied to a command decoder 24 and a data comparator 23.
The information ("0"/"1") read from memory array 19 is read by sense amplifier 16 through Y gate 9, and provided as an RD signal to data terminal 27 through an output buffer 2. The Y gate 9 for selecting an arbitrary bit line is selected by an Y address signal. Namely, the Y address signal is input to Y address buffer 4, predecoded by Y predecoders 5 and 6, and further decoded by Y decoder 7. Thus any of the Y gates selected through Y driver 8 is turned on.
An arbitrary word line is selected by an X address signal. The X address signal is input to X address buffer 10, predecoded by X predecoders 11, 12 and 13, and further decoded by an X decoder 14. Thus the word line selected through word driver 15 is raised to the "H" level.
In a flash memory, it is necessary to set the selected bit line to a high voltage, and the selected word line to the high voltage also during writing operation, as will be described in detail later. Y driver 8 and word driver 15 have the function of converting the power supply voltage to a high voltage. An erasing circuit 18 controls source line potential of memory array 19. Erasing circuit 18 is controlled by an internal control signal such that a high voltage is applied to the source line of the memory array 19 in erasing operation, and the source line of memory array 19 is grounded in reading and writing operations.
ACE buffer 20 is a buffer of an external control signal for activating the flash memory, a WE buffer 21 is a buffer for an external control signal for controlling command input mentioned above, and an OE buffer 22 is a buffer for an external control signal controlling an output buffer 2 for externally reading the data. A voltage control circuit 26 is for converting an externally applied high voltage to another high voltage required in a device.
Writing and erasing operations are performed in accordance with flow charts shown in FIGS. 23 and 24 which will be described later, while performing internal address generation, voltage control and so on. Such control is performed by a sequencer 25 receiving, as inputs, signals from a command decoder 24. Sequencer 25 includes an address generator, an operation control circuit, a pulse application number counter and so on. Details of these components are not given, since they are not directly related to the present invention.
FIG. 14 shows a specific structure of the Y gate and the memory array shown in FIG. 13. FIG. 15 shows memory cells of FIG. 14 extracted, FIG. 16 shows reading, programming and erasing potentials, and FIG. 17 also show the potentials in a table.
Referring to FIGS. 13 to 17, memory array structure, voltage conditions for writing and erasing operations and principle of operation of the memory cell will be briefly described. FIG. 14 shows memory array 19 including 32 bits of memory cells. Drains of the memory cells are connected to bit lines 227 to 234, respectively. Of the bit lines 227 to 230 of I/O1 and bit lines 231 to 234 of I/O0, only one arbitrary bit line is connected to sense amplifier 16 and program circuit 17 for every I/O, in accordance with signals 201 to 204 from Y gate 9 (obtained by decoding Y address signal). Control gates of the memory cells are connected to word lines 205 to 209, respectively, and of the word lines 205 to 209, an arbitrary word line is selected in accordance with the X address signal.
When a Y gate line 201 shown in FIG. 14 is selected, Y gates 210 and 214 are selected, and bit lines 227 and 231 are connected to the corresponding sense amplifier 16 and program circuit 17. These sense amplifiers 16 and program circuits 17 operate simultaneously. Though 2 bits constitute a word in the example shown in FIG. 14, generally one word is constituted by 8 bits/16 bits. Therefore 8 sets or 16 sets of such structure are provided. A source line 235 of the memory cells is commonly connected to the source of all the memory cells, and connected to erasing circuit 18.
FIG. 15 shows memory cells 218, 219, 220 and 221 extracted from FIG. 14. Referring to FIG. 15, the principal of respective operations of the memory cells will be described. Here, description will be given with respect to memory cell 218. FIG. 17 collectively shows voltage conditions for respective operations. In the writing operation high voltage of about 6 V is applied to bit line 227, a high voltage of about 10 V is applied to word line 205, and source line 235 is grounded. Under such voltage condition, a large current flows between the drain (bit line) and the source (source line) of the memory cell, resulting in generation of hot electrons near the drain of the memory cell. The hot electron has high energy, and further, dependent on the potential at the control gate (word line), electrons are injected to the floating gate with a certain probability. Then, the threshold voltage of the memory cell viewed from the control gate shifts to a higher value by the amount of charges of the moved (injected) electrons. The electrons once injected to the floating gate are maintained in the normal state, as the floating gate is electrically insulated.
In the erasing operation, the source line is set to a high voltage of about 9 V, the word line is grounded, and the bit line is set to a floating state. Then, a high electric field is applied between the source-control gate of the memory cell, electrons are drawn out from the floating gate because of tunnelling, and as a result, the threshold voltage viewed from the control gate lowers by the amount of extracted charges. In this manner, by applying a high voltage to the source line 235, electric field is generated in every memory cell of memory cell array 19, and thus all memory cells are erased simultaneously.
Hatched portions of FIG. 16 represent the threshold voltage of the memory cell viewed from the control gate in the writing/erasing operations, taking into consideration variations in the memory array. Here, it should be noted that the threshold voltage of the memory cell in the erase state is not lower than 0 V. A memory cell having the threshold voltage lower than 0 V (depletion) is referred to as an "over erased bit", and causes disadvantages which will be described below.
In the reading operation, a bias potential of about 1 V is applied to the bit line, a reading potential of about 5 V is applied to the word line, and the source line 235 is grounded. Referring to FIG. 16, when a memory cell to which writing has been effected is read, current does not flow even when a potential (1 V) is applied to the drain (bit line), since the threshold voltage of the memory cell is higher than the reading potential (word line potential). When a memory cell to which erasure has been effected is read, current flows between the drain and the source when a potential (1 V) is applied to the drain (bit line), since the threshold voltage of the memory cell is lower than the reading potential (word line potential). Whether the current flows or not is sensed by sense amplifier 16, and thus information is read.
In this manner, since whether a current flows through the memory cell or not is detected, when there is an over erased bit having depleted threshold voltage, current flows through the over erased memory cell, and hence information cannot be correctly read.
Referring to FIG. 17, erase verify (ERS VERIFY) and write verify (PGM VERIFY) represent reading operations for verifying sufficient shift of the threshold in respective operations. In write verify, the word line potential is set higher than the normal reading potential so as to let the current flow easier, and the content of the memory cell is read. In erase verify, the word line potential is set lower than the normal reading potential so as to suppress current flow, and the content of the memory cell is read. By such reading operations, there are provided margins with respect to the normal reading operation, as indicated by erase verify and program verify in FIG. 16.
FIG. 18 shows a path from an input of the X address signal to selection of a word line. In reading and writing operations, it is necessary to externally provide an address signal, and therefore an CTRL-AG signal of X address buffer 10 is set to the "H" level. In response to the CTRL-AG signal, in X address buffer 10, a complementary signal of the address signal is generated and provided to X predecoder 11. In erasing operation, when an operation called "write before erasure", that is, writing operation to every memory cell, is to be performed, an address is generated by internal sequencer 25, the CTRL-AG signal attains to the "L", and the external signal is cut and switched to an internal signal intA.
Address signals are divided into several groups, and predecoding is performed group by group. X predecoder 11 is a circuit for activating (setting to the "H" level in FIG. 18) only one of the output signals PR10 to 13 selected by the input address. Namely, one signal is always selected in response to an arbitrary address input. In the erasure operation, it is necessary that all word lines (control gates) are grounded (non-selected state). Therefore, a predecoder inactivating signal CTRL-ERS is input to X predecoders 11 to 13. When the CTRL-ERS signal is at the "H" level, predecoding is effected. When it is at the "L" level, all outputs PR10 to 13 are inactivated ("L" level) regardless of the address signal. In this manner, signals PR10 to 13, PR20 to 23 and PR30 to 37 predecoded by X predecoders 11, 12 and 13 are input to X decoder 14. Here, X predecoder 12 does not have the function of inactivation, and the circuit structure as the decoder is the same as that of X predecoder 11.
X decoder 14 receives predecode signals PR10 to 13, PR20 to 23 and PR30 to 37 as inputs, and activates (set to the "L" level) an arbitrary output signal. At this time, when signals are all inactive in any of the predecode signal groups (PG10 to 13, PR20 to 23 and PR30 to 37 constitute three groups), the output signal is not activated by X decoder 14 (erasing operation).
In response to the last selected output signal, word driver 13 activates the word line. At this time, when the power supply VPWL of word driver 15 is at the power supply voltage Vcc, word lines WL0 to WLn rise to the power supply voltage, and when VPWL is higher than the power supply voltage, word lines WL0 to WLn rise to that potential. Namely, in the writing operation, the power supply VPWL is set at about 10 V, and the selected word line rises to the level of 10 V. It goes without saying that at this time, the non-selected word lines are at the ground potential.
As to the path for selecting Y gate 9, the circuit structure is the same except that the word line of FIG. 18 is replaced by a Y gate line.
FIG. 19 shows a circuit structure of a write circuit, an erase circuit, Y gate and part of the memory array. Referring to FIG. 19, writing operation at the bit line will be briefly described, as well as the erasing operation. A signal WD input from input buffer 1 is applied to write circuit 17. In the writing operation, the VPBL power supply is set at a high voltage so that the bit line has the potential of 6 V, and control signal CTRL-PGM is set to the "H" level. By this setting, the sense amplifier 16, which is the reading circuit, is separated, and program circuit 17 is connected to Y gate 9. Control signal CRTL-ERS is set to "H" level, and the source of the memory cell is grounded. When the WD signal is at "L" level, 6 V is applied to the selected bit line, and when the WD signal is at the "H" level, the selected bit line is kept grounded. In this manner, since the bit line potential can be set by the input data (WD), an arbitrary data from "00h (h indicates hexadecimal notation)" to "FFh" can be written (in case a word is constituted by 8 bits). In order to avoid a high voltage remaining on the bit line after the end of writing, the CTRL-BLRST signal is controlled such that a bit line is set to the ground potential after writing operation.
In the erasing operation, the CTRL-ERS signal is set to the "L" level, and the potential set by the power supply VPSL is applied to the source line of memory array 19. Further, it is necessary to set the bit line to the floating state. This can be done by inactivating (setting to the "L" level) all the Y gate lines. Therefore, utilizing the inactivating function mentioned above, all the Y gates are inactivated by Y predecoders 5 and 6 of the Y address.
FIG. 20 is a schematic diagram showing the Y gate, the memory array and the sense amplifier, and FIG. 21 shows characteristics of nodes 602 and 603 of the sense amplifier shown in FIG. 20.
Referring to FIGS. 19 to 21, reading operation at the bit line will be described. When CTRL-PGM signal is set to the "H" level, program circuit 17 is separated from Y gate 9, and when CTRL-SE signal is set to "L", sense amplifier 16 is activated. The characteristic of the node 603 with respect to the node 602 of a p channel load type inverter formed by transistors 604 and 605 is as shown by A of in FIG. 21. The characteristic of the node 602 with respect to the node 603 of the source follower circuit formed by transistors 607, 608 and 609 as well as the memory cell is as shown by B of FIG. 21. In FIG. 21, there are two lines indicated by the character B, which correspond to the programmed state and erased state of the memory cell. The input 602 of the inverter is the output on the side of the source follower, and the output 603 of the inverter is the input to the side of the source follower, and therefore they can be plotted on the same graph. Further, cross points of characteristic curves A and B represent operational points, indicating the potentials at respective nodes. As can be seen from the graph of FIG. 21, the potential at node 602 is almost determined by the logic threshold voltage on the side of the inverter, and the value hardly fluctuates. The potential of node 602 is connected to the bit line through Y gate 9. Therefore, by setting this potential at about 1 V, the bias potential of the bit line is set to 1 V. In this state, when there is no current flowing through the bit line, the node 601 is gradually charged as shown by the curve of node 601 at the programmed state, while in the erased state in which current flows to the bit line, the node 601 is discharged almost to the bit line potential. This change is amplified by the logic gate at the output stage of sense amplifier 16, and transmitted as output signal RD, to output buffer 2.
FIG. 23 is a flow chart showing the writing operation utilizing the above described various operations, and FIG. 24 is a flow chart showing the erasing operation. In FIGS. 23 and 24, command inputs are not shown.
Referring to FIG. 23, the writing operation will be described. In the writing operation, after a command signal is input, the data input to data input terminal 27 is latched by data latch 3, and in accordance with the data, write pulse is applied to respective bit line. Then, comparison between the written data and the read data is performed by data comparator 23 shown in FIG. 13 so as to execute write verify, and when the data coincide with each other, the operation terminates. If not, write pulse is again applied. The above described writing operation is repeated until the data coincide with each other, that is, until the data pass the verifying operation.
In erasing operation, after command input, data of "00h" is written to all the memory cells which are to be erased. This is a counter measure against over erasure mentioned above. This is to suppress variation of threshold voltages of the memory cells, utilizing the characteristic that the amount of shift of the threshold voltage in writing operation saturates with time. Then, an erasure pulse is applied, and then erase verify is performed. During the erasing operation, an address signal is generated internally, and if the selected address passes the verifying operation, the address is incremented successively, repeating the verifying operation. The operation terminates when the last address is verified. When a non-erased memory cell is found during the verifying operation, erasure pulse is again applied, and the flow returns to the verifying operation. Sequencer 25 performs control of address generation, voltage control, operation branching based on data comparison and so on, in accordance with the flow charts of FIGS. 23 and 24.
FIG. 25 shows relation between the distribution of threshold voltages of the memory cells and the erase verify voltage at the time of erase verify operation. As described above; conventionally, the upper limit of the threshold voltage distribution of the memory cells in the erasing operation is detected by the verifying operation during erasure, as shown in FIG. 25(a). However, the width of distribution cannot be made narrower than the memory cell characteristics (variation of threshold voltages). Therefore, even if the lower limit of the threshold voltage distribution of the memory cells is approximately 0 V, the upper limit inevitably corresponds to the upper limit of variation of the memory cell characteristics. Accordingly, it is possible that there is no read margin at the time of low voltage operation using the power supply voltage of 3 V, for example, as shown in FIG. 25(b).
Therefore, an object of the present invention is to provide a non-volatile semiconductor memory device in which distribution of the threshold voltages of the memory cells at the time of erasure is made narrower so as to allow stable reading even when the power supply voltage is lowered. Briefly stated, the present invention provides a non-volatile semiconductor memory device including: a plurality of memory cells arranged in a matrix of rows and columns, each having a control gate, a floating gate, a source and a drain, for holding information charges at the floating gate; a plurality of bit lines provided corresponding to the rows of the memory cells and connected to the drains of the memory cells of the corresponding row; a plurality of word lines provided corresponding to the rows of the memory cells in a direction crossing the bit lines, and connected to the control gates of the memory cells of the corresponding column; a source line connected to the sources of the memory cells; an erasing circuit for extracting electrons from the floating gate; a write circuit for injecting electrons to the floating gate; and a second reading circuit for applying a positive bias voltage to the source line for reading the charge holding state of the memory cell.
Therefore, in the present invention, by applying a positive bias voltage to the source line, an over erase bit can be temporarily masked and detected.
In a preferred embodiment, the memory device further includes a level shift circuit, which includes a first logic circuit operating at a first power supply voltage and a first ground potential; a second logic circuit operating at a second power supply voltage and a second ground potential; and a capacitor element connecting an output terminal of the first logic circuit with an input terminal of the second logic circuit.
According to another aspect of the present invention, the non-volatile semiconductor memory device includes: a plurality of memory cells arranged in a matrix of rows and columns, each having a control gate, a floating gate, a source and a drain, for holding information charges at the floating gate; a plurality of bit lines provided corresponding to the rows of the memory cells and connected to the drains of the memory cells of the corresponding rows; a plurality of word lines provided corresponding to the rows of the memory cells in a direction crossing the bit lines, and connected to the control gates of the memory cells of the corresponding columns; a source line connected to the sources of the memory cells; an erasing circuit for extracting electrons from the floating gate; a first writing circuit for injecting electrons to the floating gate; a reading circuit for reading charge holding state of the floating gate; and a second writing circuit for applying a positive bias voltage to the source line for writing to the memory cell.
Therefore, in the present invention, since a positive bias voltage is applied to the source line for writing to the memory cell, an over erase bit can be repaired, and the threshold voltage distribution of memory cells at the time of erasure can be narrowed.
In accordance with a still another aspect of the present invention, the non-volatile semiconductor memory device includes: a plurality of memory cells arranged in a matrix of rows and columns, each having a control gate, a floating gate, a source and a drain, for holding information charges at the floating gate; a plurality of bit lines provided corresponding to the rows of the memory cells and connected to the drains of the memory cells of the corresponding rows; a plurality of word lines provided corresponding to the rows of the memory cells in a direction crossing the bit lines, and connected to the control gates of the memory cells of the corresponding columns; a source line connected to the sources of the memory cells; a writing circuit for injecting electrons to the floating gate; a predecode circuit for predecoding an address signal; a decode circuit for selecting an arbitrary word line in accordance with the predecode signal; a reading circuit for reading charge holding state of the floating gate; a logic inverting circuit for inverting the logic of the predecode signal; and an activating circuit for activating the predecode signal regardless of the address signal.
Therefore, in the present invention, since the logic of the predecode signal is inverted and the predecode signal is activated regardless of the address signal, only a part of the memory array can be erased, and hence a smaller erase unit can be set.
According to a still further aspect of the present invention, a method of erasing data in a non-volatile semiconductor memory device including a plurality of memory cells, a plurality of bit lines, a plurality of word lines, a source line, an erasing circuit, a first writing circuit, a first reading circuit, a second reading circuit and a second warning circuit includes a first step of determining, after erasure operation, whether the charges read by the second reading circuit is not larger than a first information charge amount; a second step of determining, after the first step, whether the charges read by the second reading circuit is not larger than a second information charge amount; and a third step of injecting, after the second step, electrons to the memory cell by the second writing circuit, to an amount larger than the second information charge amount.
Therefore, in the present invention, when it is determined that the amount of charges in the memory cell is not larger than the first information charge amount after the erasing operation and then it is determined that the amount of charges in the memory cell is not higher than the second information charge amount, electrons are injected to the memory cell to exceed the second information charge amount, so that the threshold voltage distribution in the erasing operation can be narrowed, the upper limit of distribution can be lowered by the amount of narrowing, and therefore there can be a margin even for the reading with low voltage.
Further, in still another aspect of the present invention, the method of erasing data in a non-volatile semiconductor memory device including a plurality of memory cells, a plurality of bit lines, a plurality of word lines, a source line, an erasing circuit, a first writing circuit, a first reading circuit includes a first step of determining, after erasing operation, whether the charges read by the first reading circuit is not larger than a first information charge amount, and a step of injecting, after the first step, electron to the memory cells by the second writing circuit, to an amount larger than a second information charge amount.
Therefore, in the present invention, if it is determined after erasing operation that the charges in the memory cell is not higher than the second information charge amount, electrons can be injected to the memory cell so that the amount exceeds the second information charge amount.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.